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Altera_Forum's avatar
Altera_Forum
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14 years ago

signed to unsigned

i, i want to convert a 10 bit signed into a 8 bit unsigned. i tried with the altbus, but when implemented if i input -32 i get FF instead of 0. Is there an other block? which settings i have to m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

thank you schmalish for your support.

I think that a tool where implementation differs from simulink simulation is a bad tool.

In Xylinx System Generator this type of thing doesn't happen!

I spent a lot of time for this matter.

Anyway how do you simulate VHDL?