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Altera_Forum
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17 years ago

Signal Tap and Quartus II FItter

Hi, I've completed a simulation scheme and everything is working. Now I have to test it on my Altera DE2 board so i've changed my scheme with real GPIO input and a signal tap block at the end o...
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Altera_Forum
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15 years ago

Hi Beholder,

you should be carefull adding to much signals to the SignalTap. Depending on your clock frequency (here it is like a samplerate) the Tap could use a lot of memory bits or M9k-Blocks which normally come to an end first. After Analysis & Synthesis you can take a look in your compilation report. Here you can see how many bits go down to SignalTap, even if it is not fitted. I would slow down the frequency of your sample clock if your IOs are not so fast. When the desgin is fitted you can see how many blocks & bits are used under "RAM summary" in the compilation report.