Honored ContributorHello everyone!
I am working with a Stratix III EP3SE260F1152C3 FPGA doing my PFC (final career project) I need to generate a shift register using MLAB memory but Quartus II MegaWizard Plug-in Manager only allows to use 8LUT. How can I obtain my aim?:confused: Thank you very much!
Honored ContributorI'm not sure it's possible to do a shift register with MLAB. Why do you want to do that?
Honored ContributorThe reason why I want that aim is that I need a component like Xilinx SRL16. It is a reconfigurable LUT that I can use like a 16 shift register.:(
That is why I want to use Altera shift register implemented with MLAB memory instead of 8 LUTs. Thank you very much for your help!Honored ContributorWhat's wrong with LUTs? Are you low on resources?
Honored ContributorYes, of course. I have scanty resources because i am doing CFD processing and I can´t allow use so many LUTs
Honored ContributorQuartus synthesis will automatically infer large shift-registers into memories. You can also manually create altshift_taps megafunctions. Note that this is not the same thing as the SRL16. Most importantly, it can't dynamically change the tap length, so if you use the SRL16 with dynamically change shift lengths, it's not equivalent. The altshift_taps is literally a memory with a continuously running read and write pointers(the pointers are made out of logic). So if you're doing a small, narrow shift register, then logic is better. But as soon as they get wide and/or somewhat deep, altshift_taps works better.
Honored ContributorThank you very much, Rysc!
I have tested altshift_taps but this option consumes greater memory (one lut but a lot of memory and registers) than synthesizing a shift register with several stages of pipeline. I need to use a LUT like a 16 shift register like Xilinx SRL16 does. Any solution?Honored ContributorWhat width/depth of shift register are you building? What device? For wider/deeper(say 8 bits wide, 8 bits deep), the altshift_taps consumes less resources than Xilinx. Cyclone devices may not be as much of an advantage since they don't have small memories. But really, you're storing a lot of data, so registers or memories are the two ways to get this done. I just want to make sure your analysis is correct, since I've seen designs being converted from X where they complain about this, but when it's all done it works out.
Honored ContributorEstimated Rysc,
I need a shift register with an input bus of 32 bits of data and 70 pipeline stages. I am using a Stratix III device. Thank you.Honored ContributorForget my comment about 8x8 being the approximate size where altshift_taps is better. Still, for that size, the number altshift_taps is definitely what you want. I think it's still going to be bigger than an SRL16 implementation, but hopefully not too bad(and significantly smaller than making it out of registers).
Honored Contributor
