Honored Contributor
Honored Contributorkrasner and dsl,
Thank you very much for your help. I have figured it out how to fix the board. Just left it resting without the battery for the weekend and on the morning it simply worked. That being said, the RIFFA solution worked very very well: https://www.alteraforum.com/forum/attachment.php?attachmentid=10992 So if there's someone who has a board that can use this framework, go for it! Works like a charm, and it abstracts the PCIe from your verilog code too: --- Quote Start --- On the hardware side, users access an interface with independent transmit and receive signals. The signals provide transaction handshaking and a first word fall through FIFO interface for reading/writing data. No knowledge of bus addresses, buffer sizes, or PCIe packet formats is required. Simply send data on a FIFO interface and receive data on a FIFO interface. RIFFA does not rely on a PCIe Bridge and therefore is not subject to the limitations of a bridge implementation. Instead, RIFFA works directly with the PCIe Endpoint and can run fast enough to saturate the PCIe link. Both the software and hardware interfaces have been greatly simplified. --- Quote End --- :) :) :)
