SGDMA to SDRAM speed?

It's a DE2i-150, which holds a EP4CGX150DF31C7 fpga.

I've tried putting together what you have said, but the same problem happened on the board. Except that this time, the BIOS does not seem to be loading anymore, since the self test is not running anymore (or at least, the buzzer is not buzzing). And I don't know how to fix it. Ive already tried removing the BIOS battery, which worked last time.

The FPGA is still working (I can upload other designs into it), which makes me think that it was not a pinning problem or anything like that. I have no idea what may have caused it. Just the fact that I've splitted the SGDMA into a mSDGMA caused that. Funny thing is that the last design that you have sent is supposed to run on this exact same board. But I've noticed one slight detail on the pin planner. On this design, they use the HSMC reserved clock as an 125MHz clock. I think that's not allowed, as I've looked into the board system manual and it says there that it's a "Dedicated clock input" for the HSMC.

This incompatibility does not make sense for me.

I'm not sure how to proceed now. I've already contacted the TERASIC support.