Honored Contributor
Honored Contributorkrasner,
I've tried doing what you said, using mSGDMA. I think I've done something veeery wrong, because my board actually stopped working until I've reset the BIOS (I even thought I had lost it :( ). Before putting in the FIFOs, I've done the basic scheme, using the dispatcher and the read / write masters. Here is the qsys scheme I've done for this: ht tp://1dr v.ms/1IpfnYH Notice that I've removed the old PLL, and now I'm using the pcie_core_clk, which provides 125MHz, on the DMA and SDRAM. I did that because the TimeQuest said it was not possible to get the 150MHz I was willing for. I've also uploaded the new qsys on the same folder as before in case someone wants to take a look: ht tp://1dr v.ms/1E91SZd dsl, Where should I put the dma descriptors? I'm very new, so sorry if that's a stupid question. Notice that I'm not interested in using the onchip memory, but only to speed up the SDRAM. Also, I've tried using bursts but I don't understand how to use it. Everytime I activate burst transfers on the DMA, my host application stops being able to communicate with the FPGA. Just to clarify, I'm using the Jungo Windows driver provided with the board. It works fine with the DMA scheme I've been using, but I'm getting these slow transfers I've been talking about. Is there any chance that the problem is actually in the driver? Hope you guys still have some patience to help me. Many thanks.
