SGDMA Polling Mode

By host memory I mean SDRAM connected to the host. It's common to have the SGDMA in the FPGA fetch descriptors and data from the host memory. I only mentioned this to put the polling mode into context since if you are using Nios II enabling polling doesn't really make sense since you have a low latency connection to the SGDMA CSR port using Nios II (so it's quick to get the SGDMA started back up again).

The constraints have more to do with PCIe and the host itself. For example you need to make sure when you pass pointers to the SGDMA that they are phyical memory locations and not virtual address since the SGDMA doesn't have access through the CPU MMU. With PCIe I think there are limitations on bursting across boundaries, I don't know the details about that one.

In general with the descriptors the only constraint is that they need to be placed on 32-byte boundaries in order for the SGDMA engine to fetch them correctly.