set_max_delay / set_min_delay & set_output_delay query

I tried constraining the following using set_max_delay & set_min_delay flash_nce output port :

set PERIOD_CLK 100.000

create_clock -name {clk} -period $PERIOD_CLK -waveform { 0.000 50.000 } [get_ports {in_clk}]

create_clock -name {clk_virt} -period $PERIOD_CLK -waveform { 0.000 50.000 }

set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_nce] 70

set_min_delay -from [get_ports {in_clk}] -to [get_ports flash_nce] 50

Note: Suggestion in one of the PFL documents was to constrain eg flash_nce using set_max_delay. Had to also add set_min_delay constraint because it was reported as partially constrained.

However, STA (Static Timing Analyzer) tool still reported 'unconstrained output port within unconstrained paths/summary section.

Had to add the following too to resolve the 'no output constraint on flash_nce' :

set output_max 70.0
set output_min 50.0

set_output_delay -clock clk_virt \
-max $output_max \
[get_ports flash_nce]

set_output_delay -clock clk_virt \
-min $output_min \
[get_ports flash_nce]

--

Same with the following constraint :

create_generated_clock -name dclk1 -source [get_ports in_clk] -divide_by 1 -invert [get_ports fpga_dclk]

It still reported 'No output delay was set on output fpga_dclk port. This port has clock assignments'

Can I ignore this warning ?

Please comment here.