Contributor
Super ContributorIn your equations, you're missing the clock skew, the difference between the clocks arriving at the FPGA and the downstream (output) device. So the equations should be (given that you know that downstream device's Tsu and Th):
output max = data trace (max) - clock skew (min) + Tsu
output min = data trace (min) - clock skew (max) - Th
It's OK if the min value is negative.
ContributorHi @sstrell
>> output min = data trace (min) - clock skew (max) - Th
Is this right?
Shouldn't it have been :
output min = data trace (min) - clock skew (max) + Th
Super ContributorNo, it's correct. You subtract the hold requirement to get the smallest amount possible (-min), even if it's negative.
And clock uncertainty constraints are used to describe the properties for a clock. They don't constrain a clock directly.
