Serialite II Issue

Hi,

Thanks for your update. I can understand the effort requires to create test design to help narrowing down the potential root causes. For your information, with the whole system hooked up, it is rather difficult to debug and narrow down. This is why I am suggesting that we perform a loopback at the FPGA1 where you suspect the issue coming from. To avoid affect other component in the system, not sure if it is possible for you to create simple duplex SL II design in FPGA1 and perform a loopback to see if issue pops up. If we can replicate this, it would be helpful for debugging since we narrow down to FPGA1 and single SLII IP core. I understand this might require some effort to work on.

On the other hand, to avoid any further delay, I would suggest we further engage our timing team to help look into and advise if there is any potential anomaly from timing perspective. Since I am unable to duplicate case from here, would you mind to open a new Forum case with title specific to timing ie "Timing debugging required on Quartus build dependent packet issue". You may then briefly your observation where there are varitaion from build to build and mention timing analysis debugging is required. You may then let me know the case so that I can help to route to our timing team.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin