New Contributor
Regular ContributorHi,
As I understand it, you are observe intermittent issue with the SLII IP where you observe the RX received 2 EOP for every SOP after you switch from stream mode to packet mode. This seems to be dependent on Quartus builds where some builds do not exhibit the issue but some builds do. Also the failing instance seems to be random according to builds as well.
Based on this observation, this is trending towards potential timing problem. To further narrow down the issue, would you mind to try running Modelsim simulation with your design to isolate the functional issue prior to debug into timing issue.
Also, it is recommended for your to create simple test design ie with one or two instance with single lane to facilitate the debugging process.
Do you observe any timing violation or anomaly in the failing compilation?
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorFirst, from my experience, simulation is a good tool to catch logic issues, but a very poor way to debug timing issue, especially if the problem is between two different clocks. However, I have run simulation and did not see any problem. You know, running simulation over high speed serial link for reasonable during for the problem to show up is not very realistic. Sometimes, simulation takes longer than the compile time for it to show meaningful results. It is actually easier to put in signaltap to debug the problem.
Your suggestion of simplify the design does not work either. As I said, every compilation of the same design gets different results and in most cases, the problem goes away, simplified design won't reproduce the problem. And the problem only shows up in our system, which comprises of multiple boards, FPGAs and software, when running some special cases. Simplified design won't trigger the issue.
In those compilations that reproduced the problem, there is no timing violation, no unconstrained clocks, and everything looks normal.
The biggest thing getting in the way for me to debug is the source code is encrypted. There is no way for me to debug it. I can put some signals on signaltap but I don't know the logic around those signals. And again, what makes it harder is that most times, after I changed the signaltap, the problem goes away.
Thanks,
