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Altera_Forum
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16 years ago

SERDES 6.25Gbps ALT2GXB rx_freqlocked

Hi All, I have two Stratix II FPGAs (in two boards) communicating through 20 SERDES channels (Basic protocol). Usually things work fine. When one of the boards is not connected, I expect that t...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I appreciate your immediate response. That was fast!!! Thanks.

I have not enabled syncstatus signal when creating the block. I will do that and check if that solves the problem

I did check rx_errdetect earlier and found that there was no error (on particular byte lanes).

Regarding delaying rx_freqdetect, seems like it is stable and high for a very long time, even though it should not be receiving anything valid,

But I do a digital reset (after few us delay)if I find that there is no rx_freqlocked.