SDRAM Controller

Single data rate DRAM controller is available as an Altera reference design, much more complex double data rate DRAM controller as encrypted Altera IP core with user manuals, example projects, application notes and such.

have you got any document which is relative with sdr sdram controller?Can you post here?Thanks advance!

There has been an Altera White Paper sdr sdram controller from 2002 related to ref-sdr-sdram-vhdl.zip. I couldn't locate the document and the design now.

Huhu, i need it now.I'm doing final project in university.Help me, please

Either I missed the files at Altera site or they have been removed because of their age. However, I've been using a SDR controller based on this design recently.

I tried to find it on Altera's site, but I think it has been removed...I have a copy of the IP Core Manual that I renamed to sdr_sdram_tuning.pdf...It is the same manual though. I only renamed it to remind myself of the custom board pll tuning formulae that is in the appendix for phase delay shifting. Hope it can help

Thanks u very much. can you explain to me the timing diagram of each module?EX: INIT_FSM module and CMD_FSM module?The relationship of each module with Signal Generation module?

Hichic, i dont know the pinouts, timing diagram and state machine of each module: INIT_FSM, CMD_FSM, COUNTER, SIGNAL GENERATION and DATA PATH.

I was aware now, that the other SDR DRAM IP core, Daniel was referring to, is the SDRAM Controller Megafunction available with SOPC Builder. The posted document is also part of Quartus II Version 7.2 Handbook, Volume 5 Embedded Peripherals. In contrast to the old SDRAM reference design, it has an Avalon interface with a FIFO, but it's also rather simple and could be used in a standalone application.

Nobody can help me to find pinouts, timing diagram, and state machine of each modules?Help me, please!