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Altera_Forum
Honored Contributor
18 years agoI was aware now, that the other SDR DRAM IP core, Daniel was referring to, is the SDRAM Controller Megafunction available with SOPC Builder. The posted document is also part of Quartus II Version 7.2 Handbook, Volume 5 Embedded Peripherals. In contrast to the old SDRAM reference design, it has an Avalon interface with a FIFO, but it's also rather simple and could be used in a standalone application.