SDRAM Controller

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syncResetClkCNT <=# tDLY (clkCNT == NUM_CLK_READ) ? 1 : 0;Warning: truncated value with size 16 to match size of targer

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I would expect a warning value with size 32 in this case, cause integer values have 32 rather than 16 as default size.

If you examine Verilog code examples thorougly, you should notice that the bit width field of sized constants usually matches the target size.

regSysDX <=# tDLY 4'h0;

would be a matching assignment. Generally, the compiler also accepts unsized constants as in your second example, but you will get a warning then, if it isn't disabled.

By the way, the# tDLY is ignored in synthesis, it's functional in ModelSim only,