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Gyud0's avatar
Gyud0
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

SDRAM Controller FPGA IP- read x"FFFF" from the IP and not the ejected data from SDRAM

Hey,

I'm using the SDRAM Controller Intel FPGA IP for a 256Mbits device (16 bit).

When I execute a read operation via the Avalon MM interface, I see that the SDRAM eject the correct data via it's Address and data port (that connected to the FPGA), but the data that I got from the IP equales to x"FFFF" synchronized to avmm_readdatavalid pulse.

Can you help me with this problem?

Thanks

3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Gal,


    Thank you for submitting your question in Intel Community.


    I can see that you are having problem while reading from memory.

    But I need to clarify some information below.


    • Which SDRAM Controller IP that you are using?
    • Which Quartus version and edition that you are using?
    • Which device that you are working on?
    • Are you using Intel Dev Kit or your own custom board?
    • Are you using an example design or your own design?
    • Any memory datasheet and user guide that you are referring to?


    Thanks,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


  • Gyud0's avatar
    Gyud0
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hey,

    My answers:

    • Which SDRAM Controller IP that you are using? SDRAM Controller Intel FPGA IP
    • Which Quartus version and edition that you are using? Quartus 20.1 Prime
    • Which device that you are working on? Cyclone V
    • Are you using Intel Dev Kit or your own custom board? A custom board
    • Are you using an example design or your own design? No
    • Any memory datasheet and user guide that you are referring to? Yep, I'm using the MT48LC16M16A2:https://www.micron.com/-/media/client/global/Documents/Products/Data%20Sheet/DRAM/256Mb_sdr.pdf

    I'm repeating again that I see that the SDRAM eject the correct data via it's Address and data port (that connected to the FPGA- Via SignalTap), but the data that I got from the IP equales to x"FFFF" synchronized to avmm_readdatavalid pulse.