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Gyud0's avatar
Gyud0
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

SDRAM Controller FPGA IP- read x"FFFF" from the IP and not the ejected data from SDRAM

Hey, I'm using the SDRAM Controller Intel FPGA IP for a 256Mbits device (16 bit). When I execute a read operation via the Avalon MM interface, I see that the SDRAM eject the correct data via it's...
Gyud0's avatar
Gyud0
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hey,

My answers:

  • Which SDRAM Controller IP that you are using? SDRAM Controller Intel FPGA IP
  • Which Quartus version and edition that you are using? Quartus 20.1 Prime
  • Which device that you are working on? Cyclone V
  • Are you using Intel Dev Kit or your own custom board? A custom board
  • Are you using an example design or your own design? No
  • Any memory datasheet and user guide that you are referring to? Yep, I'm using the MT48LC16M16A2:https://www.micron.com/-/media/client/global/Documents/Products/Data%20Sheet/DRAM/256Mb_sdr.pdf

I'm repeating again that I see that the SDRAM eject the correct data via it's Address and data port (that connected to the FPGA- Via SignalTap), but the data that I got from the IP equales to x"FFFF" synchronized to avmm_readdatavalid pulse.