Honored Contributor
Honored ContributorHi Jake,
Sorry for my belated reply. --- Quote Start --- There are two issues at hand: 1 - You need to dedicate enough time to each master to allow efficient access of the DDR2 memory. If you just write small chunks of data and constantly switch between masters, your DDR2 efficiency will suffer and you won't be able to satisfy your bandwidth requirements. This is due to the memory controller having to switch between pages within the memory. 2 - You need to provide enough local buffering on each of the masters so that they don't overflow or underflow while the other masters are accessing the memory. --- Quote End --- How did you deal with the issue no.2? I don't have other memory resources except for a single DDR2 and FPGA on-chip memory. On-chip memory is the only option for local buffering in my case. --- Quote Start --- I have done this three different ways: 1 - SOPC builder allows you to specify priority and arbitration shares for each of the masters. You can use this to ensure that each master is guaranteed a certain number of accesses on the bus (assuming the master needs them). 2 - You can create your avalon masters to support bursts. When using bursts, the master specifies how many transfers it wishes to make. No other masters are granted access during that time. 3 - You can create your own arbitration. Mine is quite simplistic. Round Robin scheduling between the masters. Each master is guaranteed a minimum amount of transfers unless it doesn't actually need them. If none of the other masters have something to say, a master may continue to occupy the bus. This is somewhat self regulating as the DDR2 access becomes more efficient as the loading increases. --- Quote End --- I will try one after another. This is the first time I heard about 'priority and arbitration shares' between masters within the SOPC builder. Although it's self-explanatory, I will read the SOPC builder handbook... There is a customizable scheduler comes with the Microtronix SDRAM controller. Its default arbitration scheme is Round-Robin. The Microtronix's is becoming my choice provided that it's easy to simulate before being implemented into a real hardware. --- Quote Start --- The local buffering of course is usually done using FIFOs. One thing you need to do is ensure that your data transfers take full advantage of the width of your memory interface. Do not do 32-bit data transfers if your DDR2 memory is 128 bits wide. You're just killing your efficiency otherwise. Your most inefficient accesses will be your NIOS master. Give it as large of a data cache as possible. Consider using other memory for the NIOS rather than your buffering memory. --- Quote End --- Related to my first question in this post, what memory resources do the FIFOs utilitize: external resources or FPGA on-chip resources (on-chip memory, FPGA LEs, etc.)? I am considering creating burst masters with data width of 128 while the DDR2 is 64 bit wide. About the Nios, I might have to use on-chip memory. The biggest issue here is that there may be not enough on-chip mem. for both masters local buffering and Nios's program memory. --- Quote Start --- Don't know if this helps but good luck. --- Quote End --- I don't have enough words to say THANK YOU. I was relieved to hear from you. Avtx30
