Hi CheePin,
1. Are the CLKUSR and refclk to TX PLL to the SDI TX directly sourced from free-running oscillators on board? This is to ensure successful power up calibration.
I am sure that the CLKUSR and refclk to TX PLL are free running..
2. From your description, seems like the tx_pll_locked stays low. We can narrow down our focus here because without the TX PLL achieving lock, the SDI TX will not work. Just to check with you which TX PLL type are you using?
Both are using fPLL, following the reference project. HDMI is using FPLL_1CB, SDI is using 1DB
3. Can you try with the latest Q21.2Pro to see if this problem persists? This is to isolate any Quartus dependent problem and any known issue which might have been fixed from Q19.2 to Q21.2 releases.
I don't have the license for new Q Pro..
4. Is there any relation between the HDMI core and the SDI core? For example, sharing the same PLL and etc.
No, there's no relation between HDMI and SDI..
5. Please check through the Quartus compilation warnings to see if you can spot any anomaly ie TX PLL spacing rules violation and etc.
OK, I will check.. I knew there limitation about using ATX PLL but it should work for fPLL..
We noticed that when the board is up, the 1st time sof downloading, SDI is not working.
But if we download the same sof again.. SDI will be back to work..
Any thought?
BRs,
Bin