New Contributor
Regular ContributorHi Bin,
As I understand it, you observe some problems with your design with the SDI TX core. Based on my understanding, there should be no dependency between HDMI and SDI cores. To further narrow down the problem, just to check with you on the following:
1. Are the CLKUSR and refclk to TX PLL to the SDI TX directly sourced from free-running oscillators on board? This is to ensure successful power up calibration.
2. From your description, seems like the tx_pll_locked stays low. We can narrow down our focus here because without the TX PLL achieving lock, the SDI TX will not work. Just to check with you which TX PLL type are you using?
3. Can you try with the latest Q21.2Pro to see if this problem persists? This is to isolate any Quartus dependent problem and any known issue which might have been fixed from Q19.2 to Q21.2 releases.
4. Is there any relation between the HDMI core and the SDI core? For example, sharing the same PLL and etc.
5. Please check through the Quartus compilation warnings to see if you can spot any anomaly ie TX PLL spacing rules violation and etc.
Please let me know if there is any concern. Thank you.
