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Altera_Forum
Honored Contributor
Honored Contributorsdi IP core bug?
Hi,evrybody, I use EP3C5E144,use SDI core RX only,that mean it recieve the SDI and convernt to parallel signals,but the rx_clk is always keep "1",I think it should 27M clock,or not?Can you help me?
Altera_ForumHonored Contributor
Honored Contributorask altera why did they make such clock output. Anyway, I had no problems using 135MHz output.
