Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

scaler usage in run time control

I am using vip suite 9.0 and quartus 9.0 for out new project.

I am able to process frames with scaler in static parameters mode there is problem with runtime controle mode.I had following issues

1.I did not found any where a detailed procedure for giving the run time parameters.The vip suite pdf is very vague not detailed in this issue.

2.I could not able to generate the frames using the run time control i could only process single frame that too not correctly

the parameters i am giving are output width 64 and height 32 using the registers

and input width and height as 32x32 using the control packet but the problem is the core is not discarding the extra data if i gave more than 1024 pixels and the output is same size as the input

please help me regarding these issues

Regards

ysc

16 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    My first recommendation is that you do the video processing path inside SoPC builder. This will make your life significantly easier. At the very least, I would do the deinterlacer and DDR2 memory in SoPC builder.

    The MA Deinterlacer has 5 memory masters. If you do it inside SoPC builder, it will take care of the memory arbitration for you. If you do it on your own, you'll have to write a memory arbitrator.

    As far as configuring the DDR2 interface in the deinterlacer:

    - Set the Avalon-MM ports width to 64 (match your local DDR2 interface).

    - Set the FIFO depths to 128 if you are using a device family that uses M4K RAM blocks. Set it to 256 if you are using a device family that uses M9K blocks (Stratix III, Stratix IV, Cyclone III, Arria II).

    - Set the burst target to 32.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I am not using NIOS 11 can i still build the video system using SOPC.

    IF so can u help me with an example design using deinterlacer and ddr2sdram in SOPC(vhdl) but without NIOS 11.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi jake i had developed an system using sopc and ddr2 controller using sopc but i could not make out how to control the run time parameters of deinterlacer while using in sopc.can u help me out from this issue.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    What you can do is create an avalon master using the component editor. Just create it from the template without basing it on HDL code. Then when you add this component to your system, it will basically export the avalon bus out of the system and you can control it from outside. You would have had to have done something similar to get the video in and out of the system as well.

    Alternatively, you don't necessarily have to enable run-time control on the deinterlacer if you don't need it.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi jake i tried out ur method , i had a problem i could not able to get the output from sclaler while using in runtime control.

    MY system with sopc consiste of test pattern in run time and scaler in runtime,i am giving the output of test patterm directly to the scaler input and external avalon mm controllers for run time controlling and exported the scaler output using avalon sink.

    with the system i can get the output when both test pattern and scaler are constant and when test pattern in run time controlled and scaler is constant but couldn't get the output when both are are in runtime control mode.I think the input packet to scaler might be the problem from testpattern output .can u suggest me an solution.

    One more question the address width is 4 bits and datawidth 16.for scaler address width 8bits and datawidth 32bits while using them in sopc but in megawizard they are address 2 bits and data 16 bits and address 2 bits and data 32 bits. why is it so and is there any thing to take care or change in adressing while using in sopc that is different than while accessing throungh custom code.

    regards

    ysc
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    All addresses in SoPC builder are byte addresses. So for example, if you had a scaler located at base address 0; register 0 of the scaler would be located at address 0 but register 1 would be located at address 4. Maybe you could send me a screenshot of your SoPC system?

    Also, the address space of the scaler will change depending on which scaling algorithm you have selected. I think there are only 4 addresses for the bilinear and nearest neighbor algorithm but it increases for the polyphasic.

    Jake