scaler usage in run time control

My first recommendation is that you do the video processing path inside SoPC builder. This will make your life significantly easier. At the very least, I would do the deinterlacer and DDR2 memory in SoPC builder.

The MA Deinterlacer has 5 memory masters. If you do it inside SoPC builder, it will take care of the memory arbitration for you. If you do it on your own, you'll have to write a memory arbitrator.

As far as configuring the DDR2 interface in the deinterlacer:

- Set the Avalon-MM ports width to 64 (match your local DDR2 interface).

- Set the FIFO depths to 128 if you are using a device family that uses M4K RAM blocks. Set it to 256 if you are using a device family that uses M9K blocks (Stratix III, Stratix IV, Cyclone III, Arria II).

- Set the burst target to 32.

Jake