scaler problem

It's a balance between clock frequency and fifo size. Basically when you upscale, the scaler has to use the same input line of data more than once to produce the output. This will hold off the input by at least a line. If during that time your CVI FIFO overflows, then you're in trouble. Now if you're running the VIP blocks fast enough, the scaler can chew through that second line of output and start pulling data again from the input before the FIFO gets a chance to overflow.

It's actually a fairly complex calculation to find the exact frequency. Taking into account the vertical and horizontal blanking interval and the input sample frequency at exactly what point will your FIFO overflow.

However, if you always run your VIP blocks at at least 2X the input clock frequency of any standard that will be upscaled, you'll probably avoid the issue.

Jake