Scaler II vs Scaler problems

Hi Niki,

I think you will need to add a Byte Enable output port to your 32 bits master in order to write to 16 bit slaves as you require. For example:

To write to register 0 in your 16 bit slave you would write to address 0 with the bottom two bits of the byte enable turned on.

To write to register 1 in your 16 bit slave you would write to address 0 with the top two bits of the byte enable turned on.

To write to register 2 in your 16 bit slave you would write to address 4 with the bottom two bits of the byte enable turned on.

And so on. I would suggest that you always align the addresses that your master drives out to the number of bytes in the master word (i.e. use mutliples of 4 in your case), and set the byte enables relative to this. I haven't read the Avalon-MM docs in enough detail recently enough to know what will happen if, for instance, you try to write to address 2. It is possible that SOPC Builder will be very clever and write to register 1 for the bottom two byte enables, and register 2 for the top two byte enables. However, it is also possible that it would break, so unless you really need to write to addresses that are not aligned to the master word (and you don't mind trawling through the docs to check if this is allowed) I would suggest playing it safe.

Also, be careful if you are mixing dynamic and native slaves in the same system. All of the VIP cores apart from the Scaler II still use the old native addressing, and I am pretty sure that it is how the slave is delcared that defines how the master and slave communicate. For the native slaves I think that every write by the master will always write to one slave register, regardless of the relative widths and any byte enable signals you drive (but maybe drive all the byte enables high when writing to one of these cores, just in case).

Hope this helps,

Kieron