Scaler II vs Scaler problems

Hi Kieron,

You are not at all insulting my intelligence! The art of debugging is the the systematic ellimination of possibilities and it is often the small, trivial, issues that get overlooked while focussing on the main problem! (Like, is the power switched on!). Anyway, I have found the problem and it is indeed related to the Avalon Control interface.

While looking at the ST control packets on either side, I noticed that the scaler was always outputting control packets with the resolution set to 1920x1080 even through I had set the output resolution to 1280x720. It was ignoring the control port settings even though I had verified the register addresses. (The CVI FIFO overran because my system cannot handle 1920x1080 at 50/60 fps). I started looking at the actual VHDL file generated by SOPC Builder and noticed that the Scaler II has a 32-bit data interface. My system does not include a NIOS and my custom Avalon Master component has a 16-bit data bus. All of the VIP cores I am using have 16-bit data bus interfaces. I cannot remember what SOPC builder does in such a case (16-master, 32-bit slave. I'll have to read it up from the manual again), but it seems as if this does not work for Scaler II. Interestingly, I went back to my original design with Scaler I and I noticed that it also has a 32-bit data interface, but in this case the core seems happy with writing only to the lower 16 bits of each register.

I have made a quick hack to force 32-bit data writes to the scaler and now it works as it should! I will change my Avalon master to 32-data width since this seems to be the safest route.

As a final note, the VIP UG does not mention this. Neither the Scaler nor Scaler II register maps (chapter 7) mentions that the data width is 32-bits. In chapter 4, it is mentioned under Avalon-MM Slave Interfaces that the control registers width varies between cores and it then refers the reader to chapter 7. So a note there would be useful (if you have any control over that ;-)) . Most people probably use these cores in NIOS systems with 32-bit Avalon masters, but that is not always true.

Thanks again for your interest and help!

Regards,

Niki