Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi Kieron,
Thanks for the thorough explanation of the blanking option! Some clarification in the documentation would indeed be welcome. I have still not been able to solve my problem. My datapath is as follows: CVI -> DeInterlacer(MA) -> CRS -> Scaler -> CRS -> VideoOut (The system is much more complex, but I have taken out all the non-essential blocks to debug this). VideoOut is a custom IP block that does the same as CVO, but includes a tripple frame FIFO buffer and a few other enhancements I required. The above data path works fine with the original scaler. I have tried two versions with the Scaler II: CVI -> DI -> Scaler II (422 mode) -> VideoOut and CVI -> DI -> CRS -> Scaler II (444 mode) -> CRS -> VideoOut In both cases I get CVI FIFO overflows and almost no video output. I have set the options of the Scaler II to exactly the same options as I have for the Scaler. The options are as follows: Bits per symbol: 8 Symbols in parallel: 2/3 Symbols in sequnece: 1 Enable Run Time control of input/output frame size Maximum Input Frame Width: 1920 Maximum Input Frame Height: 1080 Maximum Output Frame width: 1920 Maximum Output Frame Height: 1080 4:2:2 data (in one case selected, in the other not) Algorithm: Bilinear I have not added any extra pipelining registers. I need the 1920x1080 in the final system, but for testing now the input stream is 576p50 and the output is set to 1280 x 720. I can also set the output to 720 x 576 (in other words - no scaling required) and in both cases I get the same problem with Scaler II. The original scaler works 100% in all cases. The only non-Altera block in this chain is my custom VideoOut block, but the system has been working flawlessly for a while now using the original scaler, so I have a fair amount of confidence in my custom VideoOut block. Also, I can put in a mode where it ignores all incoming data and applies no backpressure (it always asserts ready) and even then I see the CVI FIFO overflow. My next step will be to bring out the ST input and output interface flow control signals of the Scaler to debug pins so that I can see what is going on. BTW, I have Quartus 10.1, build 197 with SP1 (Full Version). Regards, Niki