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JJame30's avatar
JJame30
Icon for New Contributor rankNew Contributor
5 years ago

SATA 2 in Quartus 14.0

Hi, I am working on 2.5'' SATA II SSD (WR2SF256G-JFITI). using ALTGX ip for transceiver configuration. kindly share reference documents for configuration settings details for speed negotiation using...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Thanks for your update. Sorry as I am not very familiar with the SATA packets. However, based on the Modelsim simulation, it seems when the TX data pattern changes, the RX is capturing invalid or corrupted data. This seems strange as generally in the Modelsim simulation, we do not have SI issue.

To facilitate further debugging:

  1. Just wonder if you have had a chance to perform a loopback within the same duplex instance to see if similar issue occur? Just to further narrow down the issue.
  2. Would you mind to share with me a high level block diagram of you modules and interconnects for better understanding.
  3. Just wonder if you have had a chance to screenshot all the Native PHY status signals ie ready, reset, CDR lock, syncstatus just to ensure the XCVR is working fine.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin