Honored Contributor
Honored ContributorJackieyes,
I don't know if I can help, but I'll throw out an idea and ask for some help in return. I notice that the timing violation is between two different clock domains, as you mention. Sometimes it's okay for there to be what seems to be a violation between different clock domains, but the timing analyzer does not know that it's okay. Perhaps you have to tell the timing analyzer that it is okay for there to be a violation. You can do this by going to the timing analyzer Constraints menu and setting Set False Paths between the two clocks. Use the full clock names (they're long and weird) as they appear in your error messages. If you have trouble with this mention it back to me, and I'll look up (on my big PC not my laptop) how I did it. Of course you have to convince you that the error message is really not a real problem. *** I've been having a heck of a hard time (in Quartus 16 and 17) generating an example design. In Qsys I select the Low Latency 10G Mac and connect it up to PLLs with the right clock frequencies. Then I click on Generate Example Design. After a long wait I get an error message, and the example design generation fails. I've also tried to get 10GB Ethernet design examples many different ways (design store, Altera Wiki, etc.) and have not been able to get any example that is usable. How did you generate a 10GB design example?
