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Altera_Forum
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8 years ago

rx_pma_clk to rx_clkout setup timing viloation in the phy of LL10G_10GBASER_RegMode

Hi I genearate the LL10G_10GBASER_RegMode example design. then use the mac and phy in my project, but I found it often reports timing viloation between below clock domains in the PHY low_late...
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Altera_Forum
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8 years ago

Here are the pins in my project,

[0][1] share the ref_clk_clk1

[2][3] share the ref_clk_clk2

# Bank GXBL1E

set_location_assignment PIN_AN42 -to tx_serial_data[0]

set_location_assignment PIN_AM44 -to tx_serial_data[1]

# Bank GXBL1H

set_location_assignment PIN_R42 -to tx_serial_data[2]

set_location_assignment PIN_P44 -to tx_serial_data[3]

# Bank GXBL1E

set_location_assignment PIN_AN38 -to rx_serial_data[0]

set_location_assignment PIN_AM40 -to rx_serial_data[1]

# Bank GXBL1H

set_location_assignment PIN_R38 -to rx_serial_data[2]

set_location_assignment PIN_P40 -to rx_serial_data[3]

# refclkgxb* Settings - LVDS

# 322.265625MHz

set_location_assignment PIN_AH36 -to ref_clk_clk_1

set_instance_assignment -name IO_STANDARD LVDS -to ref_clk_clk_1

set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to ref_clk_clk_1

set_location_assignment PIN_T36 -to ref_clk_clk_2

set_instance_assignment -name IO_STANDARD LVDS -to ref_clk_clk_2

set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to ref_clk_clk_2