Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

rx phase compensation fifo

Hi there, I am working on a design uses an ALTGX IP in a Arria II GX device and got the following error in the fitting: Error: Input port CORECLK of GXB Receiver channel PCS "fiber_trx_lev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi Oliver,

We didn't check the quality of the rx_clkout because we decided to use a local clock as our core clock for several reasons besides the jitter concern. And I actually can't remember where I got this jitter concern from, it may be from some talks we had with the local tech support team from Arrow. You might want to check with Altera directly about this, maybe the pll in CDR circuit is good enough to provide the quality you want.

Regards,

Hua