rx phase compensation fifo

Hua,

Some time has gone by since your last reply in this topic and I guess most of your problems have been solved so far.

So, I think I won't make you an astonishing revelation if I confirm chrikell's last post regarding the role of phase compensation FIFO: the purpose of this block is only to pass data between two clock domains THAT HAVE THE SAME FREQUENCY. In other words, it's a phase shifter functionnaly similar to x1 PLL. I guess it's simpler for ALTERA chip designers to implement this function with registers issued from a TSMC library Design Kit instead of using PFDs, loop filters, dividers and so on... Moreover if you have to put such a function at every PCS outputs, doing it the "digital way" could save power and add robustness.

There is only one detail I can't explain in this FIFO block: the Altera AN573 mentions the phase compensation FIFO may handle 5 UI which I translate (erroneously ?) in "the RX phase comp. FIFO's depth is 5-bit" whereas you would need a single bit (or 2 at most) in the case of same frequency RD/WR signals ?

Now, reading back your post#2, I have a question regarding the RX phase comp. FIFO read clock source: you said you had the impression that the rx_clkout from the GXB had a lot of jitter. Therefore my question is "have you probed the "rx_clkout" signal ? If yes, how have you proceeded? If no, how did get this impression?".

Indeed, in a Basic/Non-Bonded/10-RX only design, I plan to use a rx_clkout port as common clock driver for the rx_corecll[9..0] inputs but also to clock the entire FPGA fabric.

You may easily understand that if I use rx_clkout as a system clock, jitter may be a severe issue... So what level of quality have you experienced with these clocks in your design ?

Regards

Oliver