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Honored Contributor
Honored Contributorrx phase compensation fifo
Hi there, I am working on a design uses an ALTGX IP in a Arria II GX device and got the following error in the fitting: Error: Input port CORECLK of GXB Receiver channel PCS "fiber_trx_lev...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If that would be the case, there would be missing some control signals (such as WrFull or RdEmpty). --- Quote End --- Agreed. That's probably why it was called "phase compensation" fifo. I wish some gurus from Altera can confirm this. And if that's the case, I will need another fifo to pass the data path cross clock domain into my core logic. Thanks again. Hua
