rx phase compensation fifo

This Mux is, as far as I'm concerned, to use the rx_clkout of transceiver0 to use as read clock of the fifo of transceiver1 (see attached pic (from Statix IV Handbook Vol 2). (Even though it makes completely sense to use use a pll to recover the clock)

The idea of that is, if I understood it correctly, if you have several transceivers in parallel being used for the same link (as in my case 10 transceivers for one 100G Ethernet link) you can use one of the clocks to drive the logic on the receiver side.

The fifo is only there to compensate for phase shifts not to compensate different frequencies. If that would be the case, there would be missing some control signals (such as WrFull or RdEmpty).

Have a look at Arria II GX Handbook Vol 2, page 2-54. I used a similar page on the stratix handbook to finally solve my problem.

Again a hint: I had some problems rerunning the fitter (start again) without resynthesizing the whole design. It seemed to me as quartus would ignore the assignments in this case.