rx phase compensation fifo

Tried that too, still doesn't work.

But from the attached screenshot, which is taken from the Arria II GX Device handbook Volume 2 Chapter 2 p.g. 2-18 figure 2-11, the MUX circled in red seems to suggest that Altera does provide the control to choose a clock from the Fabric over the clock from the CDR for the read side of the rx phase compensation fifo.

I was going to use a pll in the Fabric to attenuate the jitter in the recovered clock and then fit right back to the phase compensation fifo, so there should be a 0ppm clock difference.

Now back to my question 1 in my post 1:

1. what is the purpose of phase compensation fifo if the input and output has to use the same clock, the rx_clkout (i.e. the recovered clock)?

I thought the phase compensation fifo is the place where the rx data path crosses clock domain boundary to my core/fabric logic. Am I understanding this wrong?

Any comments will be appreciated.

Hua