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Altera_Forum's avatar
Altera_Forum
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16 years ago

rx phase compensation fifo

Hi there, I am working on a design uses an ALTGX IP in a Arria II GX device and got the following error in the fitting: Error: Input port CORECLK of GXB Receiver channel PCS "fiber_trx_lev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I doubt that this is possible. The rx_clkout is generated using the serial input stream. This depends on the tx_clk of the sending device. A PLL will probably not generate exactly the same frequency (0 PPM difference). This leads to a buffer over- or underflow in the phase-compensating fifo.

You can nevertheless try to change the "-from" field of the command to your non-gxb-clock.

Hint: As far as I know, quartus give now feedback if your assignment command point to valid ports or not. Using the assignment editor and in there the node finder can help finding the correct ports/nodes