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Altera_Forum's avatar
Altera_Forum
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16 years ago

rx phase compensation fifo

Hi there, I am working on a design uses an ALTGX IP in a Arria II GX device and got the following error in the fitting: Error: Input port CORECLK of GXB Receiver channel PCS "fiber_trx_lev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Just tried the GXB_0PPM_CORE_CLOCK assignment, it didn't work. :(. Maybe because my source of the core clock is not coming from a gxb directly.

Now, instead of driving the core clock with the recovered clock, is it possible to use a clock of the same frequency from a pll? Does Altera provide this connection?

Thanks,

Hua