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Altera_Forum's avatar
Altera_Forum
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16 years ago

rx phase compensation fifo

Hi there, I am working on a design uses an ALTGX IP in a Arria II GX device and got the following error in the fitting: Error: Input port CORECLK of GXB Receiver channel PCS "fiber_trx_lev...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi,

I don't actually know the quality of that signal since I only simulated it so far (the device (Stratix IV GT) we want to use has not yet arrived).

I hope it's not too bad since I need the clock for quite some logic ;) But I will surely have a look at that clock.

Cheers