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Altera_Forum
Honored Contributor
16 years agorx phase compensation fifo
Hi there, I am working on a design uses an ALTGX IP in a Arria II GX device and got the following error in the fitting: Error: Input port CORECLK of GXB Receiver channel PCS "fiber_trx_lev...
Altera_Forum
Honored Contributor
16 years agoHi,
I had almost the same issue as you. You can use a different clock at the output of the fifo, but it has to have exactly the same frequency (which is the case if you use the rx_clkout of gxb1 to feed gxb2). And you have to tell quartus that both clock have the same frequency (GXB_0PPM_CORE_CLOCK property). I was trying for quite a time until I found the correct syntax. Try this: set_instance_assignment -name GXB_0PPM_CORE_CLOCK ON -from "fiber_trx_lev1_aria2gx:Fiber_Lev1_Left|rx_clkout[0]" -to {the serial input port of your top level design[0]} set_instance_assignment -name GXB_0PPM_CORE_CLOCK ON -from "fiber_trx_lev1_aria2gx:Fiber_Lev1_Left|rx_clkout[0]" -to {the serial input port of your top level design[1]} (maybe you need to adapt the command a bit) The strange thing for me is that in the "-to" field you need to assign the serial input port which comes at a much higher rate. But I got it working this way. See http://www.alteraforum.com/forum/showthread.php?t=21970 for my configuration. Cheers.