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Altera_Forum
Honored Contributor
Honored Contributorrx_locktodata and rx_locktorefclk
I have a problem whit the Clock Recovery Unit. I'm using the Serial RapidIO protocol through ALT2GXB megafunction. I tried to train the CRU by asserting the rx_locktorefclk at a certain frequ...
Altera_ForumHonored Contributor
Honored ContributorYes, i expect that the transceiver will continue to work at the same frequency (125MHz) when swithing from lock-to-reference to lock-to-data, because the data are serialized (16 parallel bits to 1 bit) at this frequency (125MHZ before serialization, 2,5GHz after 8b10b encoding).
What i really want is to communicate 2 fpga with only one cable, the data one! I want that the receiver fpga recover the clock signal from data (8b10b encoded). How i can do it?
