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Altera_Forum
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15 years ago

RTL simulation with symbol converted in HDL

I have a simple project with a single schematic file that uses the 7493 counter taken from the "others | maxplus" library of symbols. It's a TTL numerated symbol that maps the old TTL discrete log...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks Thepancake,

I followed your detailed instructions and everything works fine.

It has not been necessary to rename the 7493 Verilog instance.