RTL simulation with symbol converted in HDL

looks like i was wrong, the original source is in .bdf not AHDL, this doesn't seem so bad

if you go to $QUARTUS_ROOTDIR/libraries/other/maxplus2 you'll find 7493.bdf. if you open it up you'll see the component's source. go to File > Create > Create HDL for current file and create a Verilog file. when you create the .v from the 7493.bdf in you get the following warning explaining the slash:

Warning: Design name for "7493" contains a number -- illegal for Verilog HDL and VHDL -- adding "\" in front of name

the 7493.v file looks like its just HDL for the .bdf, it doesn't instantiate any other components. add the file to your project, and Quartus should use this instead of the .bdf to compile your design, which should allow use in ModelSim (i didn't try vsim). if it doesn't work in ModelSim, rename the module from \7493 to my7493 and rename the instantiation and that should fix it