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Altera_Forum's avatar
Altera_Forum
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15 years ago

RTL simulation with symbol converted in HDL

I have a simple project with a single schematic file that uses the 7493 counter taken from the "others | maxplus" library of symbols. It's a TTL numerated symbol that maps the old TTL discrete log...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The generated code is the following.

It recalls a strange \7493 component.

Could be the backslash the problem?

Is backslash allowed in Verilog code? 

module counter_x7493(
 Reset,
 Clk,
 Q3,
 Q2,
 Q1,
 Q0
);
input wire Reset;
input wire Clk;
output wire Q3;
output wire Q2;
output wire Q1;
output wire Q0;
wire SYNTHESIZED_WIRE_0;
assign Q0 = SYNTHESIZED_WIRE_0;
 
\7493  b2v_inst(
 .RO1(Reset),
 .RO2(Reset),
 .CLKA(Clk),
 .CLKB(SYNTHESIZED_WIRE_0),
 .QC(Q2),
 .QB(Q1),
 .QA(SYNTHESIZED_WIRE_0),
 .QD(Q3));
endmodule