Forum Discussion

Honored Contributor

15 years ago

RTL simulation with symbol converted in HDL

I have a simple project with a single schematic file that uses the 7493 counter taken from the "others | maxplus" library of symbols. It's a TTL numerated symbol that maps the old TTL discrete log...

Altera_Forum

Honored Contributor

15 years ago

my guess is that the maxplus library might be originally written in AHDL which is why a gate level simulation works. you may only the have option of a post-map and a gate level simulation

what's inside the generated Verilog file?

Forum Discussion

RTL simulation with symbol converted in HDL

Recent Discussions

Agilex 7 slew rate reconfiguration

Agilex-7 AXI MCDMA for PCIe hang

Constraints not being picked for DCFIFO

Can't generate F-Tile Ethernet Hard IP Design Example

MAX10 TSE reference design