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Altera_Forum
Honored Contributor
Honored ContributorRTL simulation with symbol converted in HDL
I have a simple project with a single schematic file that uses the 7493 counter taken from the "others | maxplus" library of symbols. It's a TTL numerated symbol that maps the old TTL discrete log...
Altera_ForumHonored Contributor
Honored Contributormy guess is that the maxplus library might be originally written in AHDL which is why a gate level simulation works. you may only the have option of a post-map and a gate level simulation
what's inside the generated Verilog file?
