RGMII with the triple speed ethernet MAC core

hi,

I remember that there is register in the MARVELL PHY to control

the RGMII receive/transmit timing. You can try to see them.

regards,

--- Quote Start ---

hi,

I remember that there is register in the MARVELL PHY to control

the RGMII receive/transmit timing. You can try to see them.

regards,

--- Quote End ---

Thanks, that was it. I adjusted the tx clock to data skew and now it works perfectly :)

Marc

Yes, but remember the TSE MAC only works for RGMII Gigabit mode but not RGMII 10/100 mode for now.

Information on setting the timing of RGMII interface

6.2.1 Receive Direction

The FPGA can accept clock edge aligned input data by adding pin-delay to the data inputs

ensuring proper DDR sampling. This can be achieved by applying negative hold-time

constraints (e.g. -1.5ns) to the data input pins of the FPGA.

If the pin-delay should not be used, alternatively the PHY can be instructed to add delay to its clock output pin by setting bit 7 of the MDIO register 20. To do so, the following procedure should be followed:

• read register 20

• set bit 7 to enable rx clock pin output delay preserving all other bits

• write register 20

• Issue a software reset to the phy to apply the change, by reading register 0

(CONTROL) and writing it back with bit 15 (reset) set to 1.

6.2.2 Transmit Direction

A typical DDR output implementation supporting multiple speeds in RGMII will provide the

clock edge aligned with the data edge. However, as the board does not implement a board

trace delay, the clock needs to be shifted by 2ns to ensure proper timing at the PHY device

inputs.

This can be done by either implementing a corresponding shift in the FPGA, or by setting the integrated delay transmit option (bit 1) within the MDIO register 20 of the PHY. To set the transmit delay option, the following procedure should be followed.

• read register 20

• set bit 1 to enable tx clock pin input delay preserving all other bits

• write register 20

• Issue a software reset to the phy to apply the change, by reading register 0 (CONTROL) and writing it back with bit 15 (reset) set to 1.

Hi,

The Altera Cyclone III 120 dev kit (DK-DEV-3C120N) has the same Marvell 88E1111 PHY hooked up to the FPGA in RGMII mode. It would not transmit until I added a +2ns phase shift on the GTX_CLK signal. I'm using it with the TSE MAC, with a PLL that generates 2 125MHz clocks, one with 0 degree phase going to the TSE tx clk, another with 90 degree phase shift going to the PHY. This board also has no power up or reconfig reset, which the PHY needs.

-Paul

--- Quote Start ---

Yes, but remember the TSE MAC only works for RGMII Gigabit mode but not RGMII 10/100 mode for now.

It seemed 8.0 now support RGMII 10/100 mode now. But do we need to set something to use 10/100 mode? Or just work without do anything.

Thanks,

Hi,

You can read to a register by using this:

TSE_cmd_reg = IORD_ALTERA_TSEMAC_CMD_CONFIG(TSE_MAC_BASE);

for a write:

IOWR_ALTERA_TSEMAC_CMD_CONFIG(TSE_MAC_BASE,TSE_cmd_reg);

Jan

hey guys, has anyone tried to make the TSE work in 100base mode?

with tse 8.1.

I'm having problem to do that.

--- Quote Start ---

Hello liangbowen (http://www.alteraforum.com/forum/member.php?u=27864) I made transmition of packet with TSE in 100 mbit mode witj rgmii (q8.1 SP1)

--- Quote End ---

hi dim, did you encounter any problem? can you guide me to implement that?

what's the phy chip you are using?

thanks.