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GDagi1's avatar
GDagi1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

RGMII data not passed to AvalonST

Hi all, I am currently attempting to take in 4 bit RGMII data into my system and then modify the resulting 32 bit AvalonST data. My testbench sends this data currently and it appears as RGMII inputs...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I understand that you also contacted Arrow dFAE (Andy) for this TSE IP debug support and you also have another forum case regarding the reg_busy stuck issue.

May I suggest we consolidate all the issue into just one support case (Andy's case) for ease of discussion and debug while I close these 2 Forum cases ?

Thanks. Your sim waveform looks much better now.

  1. Again, my first question back to you is still have you generated one TSE sim example design as golden reference for that it's easier to compare the reference sim result with your design sim result.
  2. For your sim debug, you can checkout following suggestion
  • Have you run the sim longer to double confirm there is really nothing coming out to Avalon ST Rx interface ? Are you using internal FIFO in cut through mode or store and forward mode ?

Thanks.

Regards,

dlim

  • GDagi1's avatar
    GDagi1
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi again dlim,

    Your first statement regarding Arrow and the reg_busy issue is correct. We can combine these two if you'd like. Would I need to do that?

    Firstly, my reg_busy issue has been mostly resolved. I would like to focus on solving that and then moving on to the Avalon issue (if it persists). The FSM which configures the registers is being entered and I would like to monitor the behavior, but the configuration is done before the waveforms appear in simulation (the signals show as "-No Data-"). I could get around this by repeatedly entering the FSM but do not want to do that in the final design. Is there a way to start up each module simultaneously so that this offset doesn't exist? Attached is an example of this. I drive the FSM with the reg_clk.

    To answer your other questions:

    1. I have been able to generate an example which uses one Ethernet port.
    2. My current design was in cut-through mode but is now in store and forward mode (Rx_almost_empty and Tx_section_full being set to '0' in my configuration).
    3. I am using "run -all" for simulation duration.

    Thanks again