Forum Discussion
Occasional ContributorRGMII data not passed to AvalonST
Regular ContributorHi,
I understand that you also contacted Arrow dFAE (Andy) for this TSE IP debug support and you also have another forum case regarding the reg_busy stuck issue.
May I suggest we consolidate all the issue into just one support case (Andy's case) for ease of discussion and debug while I close these 2 Forum cases ?
Thanks. Your sim waveform looks much better now.
- Again, my first question back to you is still have you generated one TSE sim example design as golden reference for that it's easier to compare the reference sim result with your design sim result.
- For your sim debug, you can checkout following suggestion
- Have you run the sim longer to double confirm there is really nothing coming out to Avalon ST Rx interface ? Are you using internal FIFO in cut through mode or store and forward mode ?
- Also, just curious. Is the reg_busy issue resolved now ? Meaning you are able to configure TSE IP correctly now or else it won't work correctly
- You can review the chapter 5.3.1 (page 101) to ensure you initialize TSE IP correctly for RGMII configuration (watch out on TSE MAC reset condition and also TX, RX path enable condition)
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
Thanks.
Regards,
dlim
- GDagi1
Hi again dlim,
Your first statement regarding Arrow and the reg_busy issue is correct. We can combine these two if you'd like. Would I need to do that?
Firstly, my reg_busy issue has been mostly resolved. I would like to focus on solving that and then moving on to the Avalon issue (if it persists). The FSM which configures the registers is being entered and I would like to monitor the behavior, but the configuration is done before the waveforms appear in simulation (the signals show as "-No Data-"). I could get around this by repeatedly entering the FSM but do not want to do that in the final design. Is there a way to start up each module simultaneously so that this offset doesn't exist? Attached is an example of this. I drive the FSM with the reg_clk.
To answer your other questions:
- I have been able to generate an example which uses one Ethernet port.
- My current design was in cut-through mode but is now in store and forward mode (Rx_almost_empty and Tx_section_full being set to '0' in my configuration).
- I am using "run -all" for simulation duration.
Thanks again
