Regarding the TX settings of MIPI CSI2 IP

Hi ,

Based on what you describe, Your MIPI CSI-2 TX's ready will stay low unless the core and PHY are fully initialized, out of reset, and properly configured. Please try to check resets, clocks, core/PHY ready signals, and configuration.

The most common issue is the DPHY not being ready or the core not being enabled.
I would suggest to try generate the design example by default and try it again.
There is ready MIPI design example available, perhaps you can try out that https://github.com/altera-fpga/agilex-ed-camera-ai

Regards,
Wincent