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Altera_Forum's avatar
Altera_Forum
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16 years ago

regarding PARAMETER

Hi All, is there any possibility to use parameter selecation in place of `ifdef and `else Your timely response is very appreciated! Regards Divyesh
Altera_Forum's avatar
Altera_Forum
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16 years ago

You may want to consult your favourite Verilog text book or reference manual for the purpose of generate statement.