Reg AN427 Example Design on Quartus 9 WE

Thank you FvM!

Sorry for the dalayed reply. I changed the FPGA configuration pin settings to regular I/O and was able to fit the design.

The fitter shows Critical Warning: PLL clock inst|....|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL.

& warnings like: *alt_vip_IS2Vid:*|is_serial_output

[*] could not be matched with a keeper. (filter problem-mismatch)

After simulating altpll in Modelsim, the transcript msg reads

Note: Cyclone III PLL locked to incoming clock

I'm not familiar with pll & VIP suite and learning it. Kindly guide me.