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Altera_Forum
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17 years ago

Reg AN427 Example Design on Quartus 9 WE

I like ur input reg VIP example design: AN427 on cycloneIII EP3C120 I tried to synthesize and create programming file instead of the provided sof file. But the Analysis & Synthesis result repo...
Altera_Forum's avatar
Altera_Forum
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17 years ago

The first two warnings are assigned to particular RAM instances in your design. Check, why these instances apparently have settings, that are incompatible with Cyclone III. A warning doesn't prevent synthesis, so may simply ignore it.

The two errors are causes by your FPGA device options settings. You must specify the configuration pins as regular I/O after configuration.